High-speed devices for modular reduction with minimal hardware costs

High-Speed RSA Hardware Based on Barret's Modular Reduction Method

The performance of public-key cryptosystems like the RSA encryption scheme or the Diffie-Hellman key agreement scheme is primarily determined by an efficient implementation of the modular arithmetic. This paper presents the basic concepts and design considerations of the RSAγ crypto chip, a high-speed hardware accelerator for long integer modular exponentiation. The major design goal with the R...

High-Speed MARS Hardware

Abstract. High-speed MARS encryption/decryption hardware was developed using a 0.18μm IBM CMOS technology. In order to boost performance, a special adder and multiplier was designed by optimizing the adder block structure and interconnections between adder cells using signal delay profiles. A description of the hardware including block diagrams and data flow diagrams is presented. One of the mo...

High Speed Deep Packet Inspection with Hardware

EtherCAT | Cutting Costs with High-speed Ethernet

ARQ Protocols for High Speed Hardware Implementation

In order to fully exploit high speed communication channels the processing burden at the the end points must be reduced. One way in which this can be done is by shifting the implementation of protocols from software to specialized, dedicated hardware. This process is made easier if the the protocols are designed with hardware implementation in mind. In this paper we consider a family of ARQ pro...